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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xra1405 16-bit spi gpio expander with integrated level shifters september 2011 rev. 1.0.0 general description the xra1405 is an 16-bit gpio expander with an spi interface. after po wer-up, the xra1405 has internal 100k ohm pull-up resistors on each i/o pin that can be individually enabled. in addition, the gpios on the xra1405 can individually be controlled and configured. as outputs, the gpios can be outputs that are high, low or in three-state mode. the three-state mode feature is useful for applications where the power is removed from the remote devices, but they may still be connected to the gpio expander. as inputs, the internal pull-up resistors can be enabled or disabled and the input polarity can be inverted. the interrupt can be programmed for different behaviors. the interrupts can be programmed to generate an interrupt on the rising edge, falling edge or on bo th edges. the interrupt can be cleared if the input changes back to its original state or by reading the current state of the inputs. the xra1405 is available in 24-pin qfn and 24-pin tssop packages. features ? 1.65v to 3.6v operating voltage ? 16 general purpose i/os (gpios) ? integrated level shifters ? 5v tolerant inputs ? maximum stand-by current of 1ua at +1.8v ? spi bus interface spi clock frequency up to 26mhz ? individually programmable inputs internal pull-up resistors polarity inversion individual interrupt enable rising edge and/or fa lling edge interrupt input filter ? individually programmable outputs output level control output three-state control ? open-drain active low interrupt output ? 3kv hbm esd protection per jesd22-a114f ? 200ma latch-up performance per jesd78b applications ? personal digital assistants (pda) ? cellular phones/data devices ? battery-operated devices ? global positioning system (gps) ? bluetooth
xra1405 2 16-bit spi gpio expander with integrated level shifters rev. 1.0.0 f igure 1. xra1405 b lock d iagram spi bus inte rfa ce vcc (1.65v ? 3.6v) gnd ir q # si so cs# scl gpio control registers p0 gpios p1 p2 p3 p4 p5 p6 p7 p8 gpios p9 p10 p11 p12 p13 p14 p15 integrated level shifters (1.65v ? 3.6v) vccp ordering information p art n umber p ackage n umber o f gpio s o perating t emperature r ange d evice s tatus xra1405il24-f qfn-24 16 -40c to +85c active xra1405il24tr-f qfn-24 16 -40c to +85c active xra1405ig24-f tssop-24 16 -40c to +85c active XRA1405IG24TR-F tssop-24 16 -40c to +85c active n ote : tr = tape and reel, f = green / rohs f igure 2. p in o ut a ssignments p11 xra1405 24-pin tssop 3 5 4 7 6 8 9 10 11 12 1 2 13 14 15 16 17 18 19 20 21 22 23 24 irq# vcc si p0 p1 p2 p3 p4 p5 p6 p7 gnd vccp so scl cs# p15 p14 p13 p12 p11 p10 p9 p8 xra1405 24-pin qfn 78 9101112 gnd p8 p9 p10 p7 p6 17 18 13 16 14 15 p13 p14 p15 cs# p12 24 23 22 21 20 19 2 1 6 3 5 4 p3 p2 p1 p0 p4 p5 irq# vccp so scl vcc si
xra1405 3 rev. 1.0.0 16-bit spi gpio expander with integrated level shifters pin descriptions pin description n ame p in # p in # t ype d escription spi interface so 20 23 o spi serial data output. scl 19 22 i spi bus serial input clock. irq# 22 1 od interrupt output (open-drain, active low). cs# 18 16 i spi bus chip select. si 24 3 i spi serial data input. gpios p0 p1 p2 p3 p4 p5 p6 p7 1 2 3 4 5 6 7 8 4 5 6 7 8 9 10 11 i/o i/o i/o i/o i/o i/o i/o i/o general purpose i/os p0-p7. all gpios are configured as inputs upon power- up or after a reset. p8 p9 p10 p11 p12 p13 p14 p15 10 11 12 13 14 15 16 17 13 14 15 16 17 18 19 20 i/o i/o i/o i/o i/o i/o i/o i/o general purpose i/o p8-p15. all gpios are configured as inputs upon power- up or after a reset. ancillary signals vccp 21 24 1.65v to 3.6v vcc supply voltage for gpios. vcc 23 2 pwr 1.65v to 3.6v vcc supply voltage for spi bus interface. gnd 9 12 pwr power supply common, ground. gnd center pad - pwr the exposed pad at the bottom surface of the package is designed for thermal performance. use of a center pad on the pcb is strongly recommended for ther - mal conductivity as well as to provide mechanical stability of the package on the pcb. the center pad is recommended to be solder masked defined with open - ing size less than or equal to the expo sed thermal pad on the package bottom to prevent solder bridging to the outer leads of the device. thermal vias must be connected to gnd plane as the thermal pad of package is at gnd potential. pin type: i=input, o=output, i/o= input/output, od=output open drain. qfn-24 tssop-24
xra1405 4 16-bit spi gpio expander with integrated level shifters rev. 1.0.0 1.0 functional descriptions 1.1 spi bus interface the spi interface consists of four lines: serial clock (scl ), chip select (cs#), slave output (so) and slave input (si). the serial clock, slave output and slave input can be as fast as 26 mhz. to access the device in the spi mode, the cs# signal is asserted by the spi master, then the spi master starts toggling the scl signal with the appropriate transaction information. the first bit se nt by the spi master includes whether it is a read or write transaction and the register being accessed. see table 1 below. t able 1: spi c ommand b yte f ormat b it f unction 7 read/write# logic 1 = read logic 0 = write 6:1 command byte 0 reserved f igure 3. spi w rite 0 0 0 a3 a2 a1 a0 x d7 d6 d5 d4 d3 d2 d1 d0 scl si f igure 4. spi r ead 1 0 0a3a2 a1 a0 x d7 d6 d5 d4 d3 d2 d1 d0 scl si so after the last read or writ e transaction, the spi master will set the scl signal back to its idle state (low).
xra1405 5 rev. 1.0.0 16-bit spi gpio expander with integrated level shifters 1.1.1 spi command byte an spi command byte is sent by th e spi master following the slave address. the command byte indicates the address offset of the regist er that will be accessed. table 2 below lists the command bytes for each register. t able 2: c ommand b yte (r egister a ddress ) c ommand b yte r egister n ame d escription r ead /w rite d efault v alues 0x00 gsr1 - gpio state for p0-p7 read-only 0xxx 0x01 gsr2 - gpio state for p8-p15 read-only 0xxx 0x02 ocr1 - output control for p0-p7 read/write 0xff 0x03 ocr2 - output control for p8-p15 read/write 0xff 0x04 pir1 - input polarity inversion for p0-p7 read/write 0x00 0x05 pir2 - input polarity inversion for p8-p15 read/write 0x00 0x06 gcr1 - gpio configuration for p0-p7 read/write 0xff 0x07 gcr2 - gpio configuration for p8-p15 read/write 0xff 0x08 pur1 - input internal pull-up re sistor enable/disable for p0-p7 read/write 0x00 0x09 pur2 - input internal pull-up re sistor enable/disable for p8-p15 read/write 0x00 0x0a ier1 - input interrupt enable for p0-p7 read/write 0x00 0x0b ier2 - input interrupt enable for p8-p15 read/write 0x00 0x0c tscr1 - output three-st ate control for p0-p7 read/write 0x00 0x0d tscr2 - output three-st ate control for p8-p15 read/write 0x00 0x0e isr1 - input interrupt status for p0-p7 read 0x00 0x0f isr2 - input interrupt status for p8-p15 read 0x00 0x10 reir1 - input rising edge interrupt enable for p0-p7 read/write 0x00 0x11 reir2 - input rising edge interrupt enable for p8-p15 read/write 0x00 0x12 feir1 - input falling edge interrupt enable for p0-p7 read/write 0x00 0x13 feir2 - input falling edge interrupt enable for p8-p15 read/write 0x00 0x14 ifr1 - input filter enable/disable for p0-p7 read/write 0xff 0x15 ifr2 - input filter enable/disable for p8-p15 read/write 0xff
xra1405 6 16-bit spi gpio expander with integrated level shifters rev. 1.0.0 1.2 interrupts the table below summarizes the interrupt behavior of the different register settings for the xra1405. t able 3: i nterrupt g eneration and c learing b it b it b it b it b it i nterrupt g enerated b y : i nterrupt c leared b y : 1 0 x x x no interrupts enabled (default) n/a 1 1 0 0 0 a rising or falling edge on the input reading the gsr register or if the input changes back to its previous state (state of input during last read to gsr) 1 a rising or falling edge on the input and remains in the new state for more than 1075ns 1 1 1 0 0 a rising edge on the input reading the gsr register 1 a rising edge on the input and remains high for more than 1075ns 1 1 0 1 0 a falling edge on the input reading the gsr register 1 a falling edge on the input and remains low for more than 1075ns 1 1 1 1 0 a rising or falling edge on the input reading the gsr register 1 a rising or falling edge on the input and remains in the new state for more than 1075ns 0 x x x x no interrupts in output mode n/a gcr ier reir feir ifr
xra1405 7 rev. 1.0.0 16-bit spi gpio expander with integrated level shifters 2.0 register description 2.1 gpio state register 1 (gsr1) - read-only the status of p7 - p0 can be read via this register. a read will show the current state of these pins (or the inverted state of these pins if enable d via the pir register). reading this register will clear an input interrupt (see table 3 for complete details). reading th is register will also return th e last value written to the ocr register for any pins that are configured as outputs (ie. th is is not the same as the state of the actual output pin since the output pin can be in three-stat e mode). a write to this register has no effect. the msb of this register corresponds with p7 and the lsb of this register corresponds with p0. 2.2 gpio state register 2 (gsr2) - read-only the status of p15 - p8 can be read via this register. a read will show the current state of these pins (or the inverted state of these pins if enable d via the pir register). reading this register will clear an input interrupt (see table 3 for complete details). reading th is register will also return th e last value written to the ocr register for any pins that are configured as outputs (ie. th is is not the same as the state of the actual output pin since the output pin can be in three-stat e mode). a write to this register has no effect. the msb of this register corresponds with p15 and the lsb of th is register corresponds with p8. 2.3 output control register 1 (ocr1) - read/write when p7 - p0 are defined as outputs, they can be controlle d by writing to this regist er. reading this register will return the last valu e written to it, howeve r, this value may not be the actu al state of the output pin since these pins can be in three-state mode. the msb of th is register corresponds with p7 and the lsb of this register corresponds with p0. 2.4 output control register 2 (ocr2) - read/write when p15 - p8 are defined as outputs, they can be controlle d by writing to this regist er. reading this register will return the last valu e written to it, howeve r, this value may not be the actu al state of the output pin since these pins can be in three-state mode. the msb of th is register corresponds with p15 and the lsb of this register corresponds with p8. 2.5 input polarity inversion re gister 1 (pir1) - read/write when p7 - p0 are defined as inputs, this register inverts the polarity of the input value read from the input port register. if the corresponding bit in th is register is set to ?1?, the value of this bit in the gsr register will be the inverted value of the input pin. if the corresponding bit in th is register is set to ?0?, the value of this bit in the gsr register will be the actual value of the input pin. the msb of this register corresponds with p7 and the lsb of this register corresponds with p0. 2.6 input polarity inversion re gister 2 (pir2) - read/write when p15 - p8 are defined as inputs, this register inverts the polarity of the input value read from the input port register. if the corresponding bit in th is register is set to ?1?, the value of this bit in the gsr register will be the inverted value of the input pin. if the corresponding bit in th is register is set to ?0?, the value of this bit in the gsr register will be the actual value of the input pin. the msb of this register corresponds wit h p15 and the lsb of this register corresponds with p8. 2.7 gpio configuration register 1 (gcr1) - read/write this register configures the gpios as inputs or out puts. after power-up and reset, the gpios are inputs. setting these bits to ?0? will enable the gpios as outputs. setting these bi ts to ?1? will enable the gpios as inputs. the msb of this register corresponds with p7 and the lsb of this register corresponds with p0. 2.8 gpio configuration register 2 (gcr2) - read/write this register configures the gpios as inputs or out puts. after power-up and reset, the gpios are inputs. setting these bits to ?0? will enable the gpios as outputs. setting these bi ts to ?1? will enable the gpios as inputs. the msb of this register corresponds with p 15 and the lsb of this register corresponds with p8.
xra1405 8 16-bit spi gpio expander with integrated level shifters rev. 1.0.0 2.9 input internal pull-up enable/disable register 1 (pur1) - read/write this register enables/disable s the internal pull-up resist ors for an input. writing a ?1? to these bits will enable the internal pull-up resistors. writin g a ?0? to these bits will disable the in ternal pull-up resistors. the msb of this register corresponds with p7 and the lsb of this register corresponds with p0. 2.10 input internal pull-up enable/dis able register 2 (pur2) - read/write this register enables/disable s the internal pull-up resist ors for an input. writing a ?1? to these bits will enable the internal pull-up resistors. writin g a ?0? to these bits will disable the in ternal pull-up resistors. the msb of this register corresponds with p15 and the l sb of this register corresponds with p8. 2.11 input interrupt enable register 1 (ier1) - read/write this register enables/disables the interrupts for an inpu t. after power-up and reset, the interrupts are disabled. writing a ?1? to these bits will enable the inte rrupt for the corresponding input pins. see table 3 for complete details of the interrupt behavior for various register se ttings. no interrupts are generated for outputs when gcr bit is 0. the msb of this register corresponds with p7 and the lsb of this register corresponds with p0. 2.12 input interrupt enable register 2 (ier2) - read/write this register enables/disables the interrupts for an inpu t. after power-up and reset, the interrupts are disabled. writing a ?1? to these bits will enable the inte rrupt for the corresponding input pins. see table 3 for complete details of the interrupt behavior for various register se ttings. no interrupts are generated for outputs when gcr bit is 0. the msb of this register corresponds with p 15 and the lsb of this register corresponds with p8. 2.13 output three-state control register 1 (tscr1) - read/write this register can enable/disable the three-state mode of an output. writ ing a ?1? to these bits will enable the three-state mode for the corresponding output pins. the msb of this register corresponds with p7 and the lsb of this register corresponds with p0. 2.14 output three-state control register 2 (tscr2) - read/write this register can enable/disable the three-state mode of an output. writ ing a ?1? to these bits will enable the three-state mode for the corresponding output pins. th e msb of this register corresponds with p15 and the lsb of this register corresponds with p8. 2.15 input interrupt status register 1 (isr1) - read-only this register reports the input pins that have generated an interrupt. see table 3 for complete details of the interrupt behavior for various register settings. the m sb of this register corresponds with p7 and the lsb of this register corresponds with p0. 2.16 input interrupt status register 2 (isr2) - read-only this register reports the input pins that have generated an interrupt. see table 3 for complete details of the interrupt behavior for various register settings. the msb of this register corresponds with p15 and the lsb of this register corresponds with p8.
xra1405 9 rev. 1.0.0 16-bit spi gpio expander with integrated level shifters 2.17 input rising edge interrupt enable register 1 (reir1) - read/write writing a ?1? to these bits will enable the corresponding input to generate an interrupt on the rising edge. see table 3 for complete details of th e interrupt behavior for various register settings. the msb of this register corresponds with p7 and the lsb of this register corresponds with p0. 2.18 input rising edge interrupt enable register 2 (reir2) - read/write writing a ?1? to these bits will enable the corresponding input to generate an interrupt on the rising edge. see table 3 for complete details of th e interrupt behavior for various register settings. the msb of this register corresponds with p15 and the lsb of th is register corresponds with p8. 2.19 input falling edge interrupt enab le register 1 (feir1) - read/write writing a ?1? to these bits will enabl e the corresponding inpu t to generate an interrupt on the falling edge. writing a ?1? to these bits will make that input generate an interrup t on the rising edge only. see table 3 for complete details of the interrupt behavior for various regi ster settings. the msb of this register corresponds with p7 and the lsb of this register corresponds with p0. 2.20 input falling edge interrupt enab le register 2 (feir2) - read/write writing a ?1? to these bits will enabl e the corresponding inpu t to generate an interrupt on the falling edge. writing a ?1? to these bits will make that input generate an interrup t on the rising edge only. see table 3 for complete details of the interrupt behavior for various regi ster settings. the msb of this register corresponds with p15 and the lsb of this r egister corresponds with p8. 2.21 input filter enable regi ster 1 (ifr1) - read/write by default, the input filters are enab led (ifr = 0xff). when the input filters are enabled, any pulse that is greater than 1075ns will ge nerate an interrupt (if enabled). pulses that are less than 225ns will be filtered and will not generate an interr upt. pulses in between this range may or may no t generate an interr upt. writing a ?0? to these bits will disable the input filter for the corresponding inputs. with the input filters disabled, any change on the inputs will generate an interrupt (if enabled). see table 3 for complete details of the interrupt behavior for various register settings. the msb of this register corresponds with p7 and the lsb of this register corresponds with p0. 2.22 input filter enable regi ster 2 (ifr2) - read/write by default, the input filters are enab led (ifr = 0xff). when the input filters are enabled, any pulse that is greater than 1075ns will ge nerate an interrupt (if enabled). pulses that are less than 225ns will be filtered and will not generate an interr upt. pulses in between this range may or may no t generate an interr upt. writing a ?0? to these bits will disable the input filter for the corresponding inputs. with the input filters disabled, any change on the inputs will generate an interrupt (if enabled). see table 3 for complete details of the interrupt behavior for various register settings. the msb of this register corresponds with p15 and the lsb of this register corresponds with p8.
absolute maximum ratings power supply voltage 3.6 volts supply current 160 ma ground current 200 ma external current limit of each gpio 25 ma total current limit for gpio[15:8] and gpio[7:0] 100 ma total current limit for gpio[15:0] 200 ma total supply current sourced by all gpios 160 ma operating temperature -40 o to +85 o c storage temperature -65 o to +150 o c power dissipation 200 mw typical package thermal resistance data (margin of error: 15%) thermal resistance (24-qfn) theta-ja = 38 o c/w, theta-jc = 26 o c/w thermal resistance (24-tssop) theta-ja = 84 o c/w, theta-jc = 16 o c/w xra1405 10 16-bit spi gpio expander with integrated level shifters rev. 1.0.0
electrical characteristics dc electrical characteristics u nless otherwise noted : ta = -40 o to +85 o c, v cc is 1.65v to 3.6v s ymbol p arameter l imits r m in m ax l imits r m in m ax l imits r m in m ax u nits c onditions v il input low voltage -0.3 0.2 -0.3 0.5 -0.3 0.8 v note 1 v ih input high voltage 1.4 5.5 1.8 5.5 2.0 5.5 v note 1 v ol output low voltage 0.4 0.4 0.4 v v v i ol = 6 ma i ol = 4 ma i ol = 1.5 ma note 2 & note 4 v ol output low voltage 0.5 0.5 0.5 v i ol = 8 ma note 3 v oh output high voltage 1.4 1.8 2.0 v v v i ol = -4 ma i ol = -2 ma i ol = -0.2 ma note 2 v oh output high voltage 1.2 1.8 2.6 v v v i oh = -8 ma i oh = -8 ma i oh = -8 ma note 3 i il input low leakage current 10 10 10 ua i ih input high leakage current 10 10 10 ua c in input pin capacitance 5 5 5 pf i cc power supply current 0.5 1.0 2.0 ma test 1 i cc power supply current 0.6 1.2 2.4 ma test 2 i ccs standby current 1 2 5 ua test 3 r gpio gpio pull-up resistance 60 140 60 140 60 140 k : 100k : r 40% xra1405 11 rev. 1.0.0 16-bit spi gpio expander with integrated level shifters n ote : the vcc comes from vccp pin for the gpios and the vcc pin for the other signals; n otes : 1. for spi input signals (si, scl) & gpios, a0, a1 and a2 signals; 2. for spi output signal so; 3. for gpios; 4. for irq# signal; test 1: scl frequency is 10 mhz with internal pull-ups disabled. all gpios are configured as i nputs. all inputs are steady at vcc or gnd. outputs are floating or in the tri-state mode. test 2: scl frequency is 10 mhz with internal pull-ups enabled. all gpios are configured as inputs. all inputs are steady at vcc or gnd. outputs are floating or in the tri-state mode. 1.8v 10% 2.5v 10% 3.3v 10%
xra1405 12 16-bit spi gpio expander with integrated level shifters rev. 1.0.0 test 3: all inputs are steady at vcc or gnd to minimize stan dby current. if internal pull-up is enabled, input voltage level should be the same as vcc. scl and si are at gnd. cs# is at vcc. all gpios are configured as inputs. outputs are left floating or in tri-state mode. ac electrical characte ristics - spi-bus timing specifications unless otherwise noted: ta=-40 o to +85 o c, vcc=1.65v - 3.6v s ymbol p arameter l imits r m in m ax l imits r m in m ax l imits r m in m ax u nit c onditions f scl operating frequency 15 26 26 mhz t css cs# to scl setup time 20 20 20 ns t csh cs# to scl hold time 20 20 20 ns t do scl fall to so valid time 100 100 100 ns c l = 30 pf t ds si to scl setup time 20 20 20 ns t dh si to scl hold time 20 20 20 ns t cp scl period 66 38 38 ns t ch + t cl t ch scl high time 30 15 15 ns t cl scl low time 30 15 15 ns t csw cs# high pulse width 30 30 30 ns t d13 spi input pin interrupt clear 200 200 200 ns n ote : the vcc comes from the vcc pin. 1.8v 10% 2.5v 10% 3.3v 10%
f igure 5. spi-b us t iming t csh t css t ds t dh t cl t ch cs# sclk si so ... ... ... ... t csh t csw t do t tr f igure 6. r ead i nput p ort to c lear gpio int 0 0 a3 1 a2a1a0 x d7 d6 d5 d4 d3 d2 d1 d0 cs# scl si so t d13 int# xra1405 13 rev. 1.0.0 16-bit spi gpio expander with integrated level shifters
package dimensions (24 pin qfn - 4 x 4 x 0.9 mm ) note: the actual center pad is metallic and the size (d2) is device-dependent with a typical tolerance of 0.3mm t note: the control dimension is in millimeter. a - 0.039 - 1.00 a1 0.000 0.002 0.00 0.05 a3 0.006 0.010 0.15 0.25 t 0 14 o 0 14 o d 0.154 0.161 3.90 4.10 d2 0.087 0.102 2.20 2.60 b 0.007 0.012 0.18 0.30 e 0.020 bsc 0.50 bsc l 0.012 0.020 0.30 0.50 k 0.008 - 0.20 - xra1405 14 16-bit spi gpio expander with integrated level shifters rev. 1.0.0 inches millimeters symbol min max min max
package dimensions (24 pin tssop - 4.4 mm ) note: the control dimension is in millimeter. inches millimeters symbol min max min max a 0.031 0.047 0.80 1.20 a1 0.002 0.006 0.05 0.15 a2 0.031 0.041 0.80 1.05 b 0.007 0.012 0.19 0.30 c 0.004 0.008 0.09 0.2 d 0.303 0.311 7.70 7.90 e 0.240 0.264 6.10 6.70 e1 0.169 0.177 4.30 4.50 e 0.0256 bsc 0.65 bsc l 0.018 0.030 0.45 0.75 d 0 8 0 8 xra1405 15 rev. 1.0.0 16-bit spi gpio expander with integrated level shifters
revision history d ate r evision d escription september 2011 1.0.0 final datasheet. 16 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infr ingement. charts and schedules contai ned here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assuranc es to its satisfaction that: (a) th e risk of injury or damage has been minimized; (b) th e user assumes all such ris ks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2011 exar corporation datasheet september 2011. send your uart technical inquiry with technical details to hotline: uarttechsupport@exar.com . reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. xra1405 16-bit spi gpio expander with integrated level shifters rev. 1.0.0

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